This invention relates to program interrupt mechanisms for use in digital computers and digital data processors for generating interrupt signals upon occurrence of unusual or undesirable conditions during the execution of a computer program. This invention is particularly useful for generating a program interrupt when the computer or processor attempts to store data at a destination having a length which is less than the length of the data.
The various System/360 and System/370 computers or data processors manufactured and marketed by International Business Machines Corporation of Armonk, N.Y. (herein referred to as "IBM"), are capable of performing so-called "decimal" instructions. Among other things, these instructions enable the adding, subtracting, multiplying and dividing of numbers in a binary coded decimal format as opposed to a binary format. The machine instruction format for these decimal instructions specifies that each such machine instruction shall include an operation code, first operand starting address information, second operand starting address information, a first operand length value and a second operand length value. The length values indicate the number of bytes in the respective operands. In the execution of the decimal ADD instruction, for example, the second operand is added to the first operand and the result is placed in the first operand location. Thus, the first operand length value also represents the length of the destination at which the result is to be stored. This same consideration applies to the other decimal instructions, that is, the results of existing System/360 and System/370 decimal operations are always stored in the first operand field location.
A problem can occur and data can be lost when the length of the second operand field is greater than the length of the first operand/destination field. The field sizes alone, however, do not tell whether or not significant result digits will be lost. For example, the second operand field may be larger, but the higher order digit positions therein may only contain nonsignificant zeros. Another example is the case of subtraction. The second operand may be larger, but the subtraction process may produce a result which is not larger than the destination field length.
Various mechanisms are employed in the different System/360 and System/370 processors for producing a program interrupt for those cases where significant digits are lost because of the occurrence of an oversized decimal result. The exact nature of these mechanisms varies from one machine to the next and is dependent on the nature of the hardware circuitry in the machine. In microprogram controlled machines, this mechanism generally takes the form of a microcode routine which performs a series of microcode steps to check for the loss of significant digits.
The existing oversized result detection mechanism which appears to be most pertinent to the present invention is the one used in the IBM System/360 Model 50 processor. This Model 50 machine is described in considerable detail in the following published and copyrighted IBM Field Engineering Theory of Operation Manuals: (1) "System/360 Model 50 Comprehensive Introduction", IBM Order Number SY22-2821 (Fourth Edition copyrighted 1966); (2) "System/360 Model 50 Functional Units", IBM Order Number SY22-2822 (Fifth Edition copyrighted 1965); (3) "System/360 Model 50 RR, RX Instructions, Interruptions/Exceptions", IBM Order Number SY22-2824 (Fifth Edition dated July 1968); (4) "System/360 Model 50 RS, SI, SS Instructions", IBM Order Number SY22-2825 (Sixth Edition copyrighted 1966); and (5) "System/360 Model 50 Main Storage, Local Storage, Storage Protection", IBM Order Number SY22-2828 (Fifth Edition dated May 1969 ). Copies of these manuals may be obtained through any IBM Branch Office. The oversized result detection mechanism appears to be best described at pages 55, 56 and 68-82 of the above-indicated item (4) manual.
The IBM System/360 Model 50 machine is a microprogrammed data processor wherein the primary data buses and the arithmetic unit have a width of four bytes (32 data bits). Thus, during a given machine control cycle, the arithmetic unit can receive two 32-bit data fields and produce a 32-bit result field. In the execution of a decimal ADD instruction, for example, the general procedure is to fetch the first four bytes of each operand, add them together and store the four-byte result at the corresponding four-byte location of the first operand, and then to repeat these steps for the remaining four-byte portions of the operands until the first operand field is exhausted. Initially, the first and second operand length values are set into two individual length counters. These counters are decremented each time operand portions are passed through the arithmetic unit to reflect the number of bytes processed during that pass. The passing of data portions through the arithmetic unit continues until the first operand counter indicates that the first operand length has been exhausted. The processor then checks the second operand length counter to see if the second operand field is also exhausted. If it is, the processor proceeds to the normal instruction ending routine. If, on the other hand, the second operand length counter has not reached zero, then the remainder of the second operand field must be examined to see if it contains any significant digits. If it does, a decimal overflow interrupt is generated.
The checking of the second operand length counter and the testing of the leftover second operand digit positions for significant data requires additional machine control or microinstruction cycles.